Margin Of Error
By Ed Sperling Adding extra circuits and silicon area to a chip has always been frowned upon by chipmakers. Extra silicon means extra money, and for most chips the least expensive is always the better...
View ArticleExperts At The Table: The Growing Signoff Headache
By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product...
View ArticleMoore Memory Problems
The six-transistor static memory cell (SRAM) has been the mainstay of on-chip memory for several decades and has stood the test of time. Today, many advanced SoCs have 50% of the chip area covered with...
View ArticleHave Margins Outlived Their Usefulness?
To automate the process of solving complex design problems, the traditional approach has been to partition them into smaller, manageable tasks. For each task, we have built the best possible solution...
View ArticleWorst-Case Results Causing Problems
The ability of design tools to identify worst-case scenarios has allowed many chipmakers to flag potential issues well ahead of tapeout, but as process geometries shrink that approach is beginning to...
View ArticleMachine Learning In The Fab
Machine learning is exploding, especially where there are massive amounts of data to contend with and lots of potential interactions. This leads to two obvious insertion points in the semiconductor...
View ArticleMargin Of Error
By Ed Sperling Adding extra circuits and silicon area to a chip has always been frowned upon by chipmakers. Extra silicon means extra money, and for most chips the least expensive is always the better...
View ArticleExperts At The Table: The Growing Signoff Headache
By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product...
View ArticleMoore Memory Problems
The six-transistor static memory cell (SRAM) has been the mainstay of on-chip memory for several decades and has stood the test of time. Today, many advanced SoCs have 50% of the chip area covered with...
View ArticleHave Margins Outlived Their Usefulness?
To automate the process of solving complex design problems, the traditional approach has been to partition them into smaller, manageable tasks. For each task, we have built the best possible solution...
View ArticleWorst-Case Results Causing Problems
The ability of design tools to identify worst-case scenarios has allowed many chipmakers to flag potential issues well ahead of tapeout, but as process geometries shrink that approach is beginning to...
View ArticlePower Budgets At 3nm And Beyond
There is high confidence that digital logic will continue to shrink at least to 3nm, and possibly down to 1.5nm. Each of those will require significant changes in how design teams approach power. This...
View ArticleMulti-Physics At 5/3nm
Joao Geada, chief technologist at ANSYS, talks about why timing, process, voltage, and temperature no longer can be considered independently of each other at the most advanced nodes, and why it becomes...
View ArticleImproving Circuit Reliability
Carey Robertson, product marketing director at Mentor, a Siemens Business, examines reliability at advanced and mainstream nodes, particularly in automotive and industrial applications, what’s driving...
View ArticleLast-Level Cache
Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory,...
View ArticleMargin Of Error
By Ed Sperling Adding extra circuits and silicon area to a chip has always been frowned upon by chipmakers. Extra silicon means extra money, and for most chips the least expensive is always the better...
View ArticleExperts At The Table: The Growing Signoff Headache
By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product...
View ArticleMoore Memory Problems
The six-transistor static memory cell (SRAM) has been the mainstay of on-chip memory for several decades and has stood the test of time. Today, many advanced SoCs have 50% of the chip area covered with...
View ArticleHave Margins Outlived Their Usefulness?
To automate the process of solving complex design problems, the traditional approach has been to partition them into smaller, manageable tasks. For each task, we have built the best possible solution...
View ArticleWorst-Case Results Causing Problems
The ability of design tools to identify worst-case scenarios has allowed many chipmakers to flag potential issues well ahead of tapeout, but as process geometries shrink that approach is beginning to...
View Article
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